Write Verilog Verilog Code 4 Bit Booth S Algorithm Using Fsm Datapath Details 72 Datapath Q43793368
Write a VERILOG (verilog) code for 4 bitBooth’s algorithm using fsm and datapath. Details arebelow.
7.2 Datapath DesignTo achieve the signed binary numbermultiplication based on the Booth’s algorithm,datapath requirescertain logic blocks including;three 4-bit registers to store andan arithmetic shiftrightM, A and Q values and a 1-bit register tostore and anarithmetic shift rightQ-1value. An ALU will be used toperform arithmetic operations(A+M/A-M)and a down counter tokeeptrack of the number of operationsof FSMbased on the number ofbits that the datapath is designed for. This design should follow aparametric model so that the bit size of the multiplier can beadjusted. Firstly, use block diagram representation and design thedatapath for Boot’s Algorithm, then write a parameterizedVerilogcodeto defineyour datapath. Only 4-bit-user inputs(M andQ)are external inputs to the datapath and the CLK, RSTand the othercontrol signals should come from the FSM.
7.3FSM DesignControl unit of this datapath will be implementedby the Booths_FSMas described in the lectures. The multipliercontrol FSM will have three external input START, CLK and RST. Oncea Startsignal is received the Booth algorithm for multiplicationprocesswill start and willcontinue until n(number of bits) in thedown counter= 0.Add an asynchronous RSTsignal and out_statesignalto the design for debugging your FSM. FSM prepared in Experiment 6can help you to implement Booths_FSM. Draw the state diagram forthe FSMshowing all the inputs, outputs, and the state transitionsclearly.
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