(Solved) : Instruction Execution Design Might Always Result Stages Equal Length Example Consider Syst Q35750256 . . .
Instruction executiondesign might not always result in stages that are equal in length.As an example, consider a system that can be cleanly divided into 6stages, in the order (A, B, C, D, E, F), each with a propagationdelay (in ps) of (40, 80, 100, 150, 160, 70), for a grand total of600 ps. The register loading time is 25 ps.
(a) If you only hadone extra set of registers to place between an adjacent pair ofstages in order to form a 2-stage pipeline, where would you placethem? Compute the minimum clock cycle time and the maximum possibleCPU throughput.
(b) If you had twoextra sets of registers, where would you place them to form a3-stage pipeline? Again, compute the min clock cycle time and maxthroughput.
(c) If you had fiveextra sets of registers, and created a 6-stage pipeline, what wouldthe min clock cycle time and max throughput be?
(d) Suppose you hadtwo extra sets of registers, like in part (b). If you could directyour designers to divide any of A, B, C, D, E, F into two stages,where would you tell them to concentrate their efforts?
Expert Answer
Answer to Instruction Execution Design Might Always Result Stages Equal Length Example Consider Syst Q35750256 . . .
OR