EssayproSolutions

(Solved) : Iii Excerpt Article Preproduction Intel Xeon Phi Coprocessors Chips Provide Well One Teraf Q43909883 . . .

0. III – Excerpt of article

   “The preproduction Intel Xeon Phi coprocessors chips can providewell over one teraflop of floating-point performance. Developerscan reach this supercomputing level of number crunching power viaone of several routes:

•  Using pragmas to augment existing codes so they offload workfrom the host processor to the Intel Xeon Phi coprocessors(s)

•  Recompiling source code to run directly on coprocessor as aseparate many-core Linux SMP compute node

•  Accessing the coprocessor as an accelerator through optimizedlibraries such as the Intel MKL (Math Kernel Library)

•  Using each coprocessor as a node in an MPI cluster or,alternatively, as a device containing a cluster of MPI nodes.

  From this list, experienced programmers will recognize that thePhi coprocessors support the full gamut of modern and legacyprogramming models. Most developers will quickly find that they canprogram the Phi in much the same manner that they program existingx86 systems. The challenge lies in expressing sufficientparallelism and vector capability to achieve high floating-pointperformance, as the Intel Xeon Phi coprocessors provide more thanan order of magnitude increase in core count over the currentgeneration quad-core processors. Massive vector parallelism is thepath to realize that high performance. In a next paper, we willdiscuss how programming the Phi compares with CUDA programming.

  The Xeon Phi Hardware Model from a Software Perspective

  The Intel Xeon Phi KNC processor is essentially a 60-core SMPchip where each core has a dedicated 512- bit wide SSE (StreamingSIMD Extensions) vector unit. All the cores are connected via a512-bit bidirectional ring interconnect (Figure 1). Currently, thePhi coprocessor is packaged as a separate PCIe device, external tothe host processor. Each Phi contains 8 GB of RAM that provides allthe memory and file-system storage that every user process, theLinux operating system, and ancillary daemon processes will use.The Phi can mount an external host file-system, which should beused for all file-based activity to conserve device memory for userapplications. Even though Linux on Intel Xeon Phi provides aconventional SMP virtual memory environment, the coprocessor cardsdo not support paging to an external device.

• A preproduction card using a Knights Corner chip achieved ascore of 189 GB/s on the streams triad benchmark with ECC (ErrorCorrecting Code) enabled. It is expected the production Intel cardsshipping next month will deliver higher performance. Thetheoretical maximum bandwidth of the Intel Xeon Phi memory systemis 352 GB/s (5.5GTransfers/s * 16 channels * 4B/Transfer), butinternal bandwidth limitations inside the KNC chips (specificallythe ring interconnect) plus the overhead of ECC memory limitachievable performance to 200 GB/s or less.

• Figure 2: High-performance Xeon Phi applications exploit bothparallelism and vector processing.

  Each Intel Xeon Phi core is based on a modified Pentiumprocessor design that supports hyperthreading and some new x86instructions created for the wide vector unit. As illustrated inFigure 2, developers need to utilize both parallelism and vectorprocessing to achieve high performance. Programmers are free towork with their preferred programming languages and parallelismmodels so long as the application can scale to match Phicapabilities.

  The current PCIe packaging complicates the offload programmingmodel as external data breaks an assumption made by the SMPexecution model that any thread can access any data in a sharedmemory system without paying a significant performance penalty. Ascan be seen in Figure 3, the PCIe bandwidth is significantly lowerthan that of the on-board memory.

  So achieving high offload computational performance withexternal coprocessors requires that developers:

•  Transfer the data across the PCIe bus to the coprocessor andkeep it there

•  Give the coprocessor enough work to do

•  Focus on data reuse within the coprocessor(s) to avoid memorybandwidth bottlenecks and moving

  data back and forth to the host processor.

  Be aware that the preproduction Intel Xeon Phi cards have onlyone DMA engine, so any communications (network file-system, MPI,sockets, ssh, and so forth) between the coprocessor and host caninterfere with offload data transfers and thereby w applicationperformance.

• The key to Intel Xeon Phi floating-point performance is theefficient use of the per core vector unit. To access the vectorunit, the compiler must be able to recognize SSE-compatibleconstructs so it can generate the special Intel Xeon Phi vectorinstructions. Developers with legacy code can test if theirapplications will benefit from Xeon Phi floating-point capabilityby simply telling the compiler to utilize the SSE instructions onthe current x86 processor (through the GNU –msse or other compilerswitch). Applications that run faster with SSE (or conversely slowdown when the use of SSE instructions is disabled) will likelybenefit from the Intel Xeon Phi wide vector unit. Applications thatdon’t benefit from the SSE instruction set will be limited to theperformance of the individual Pentium-based cores. Although thismeans Intel Xeon Phi will

  probably not be a performance star for non-vector applications,these coprocessors can still be used as support devices thatprovide many-core parallelism and high memory bandwidth. “

  Figure 3: PCIe and memory bandwidths.

  While the aggregate Intel Xeon Phi computational performance ishigh, each core is slow and has limited floating-point performancewhen compared with a modern Sandy Bridge processor. Highperformance can be achieved only when a large number of parallelthreads (minimum 120) are utilized, and they issue instructions tothe wide vector units quickly enough to keep the vector pipelinefull. The current generation of coprocessor cores support up tofour concurrent threads of execution via hyperthreading. Mostdevelopers will rely on the compiler to recognize when the IntelXeon Phi special wide vector instructions can be issued to the percore vector units. (More-adventurous programmers can utilizecompiler intrinsic operations or assembly language to access thevector units.) This means that existing libraries and applicationsmust be recompiled to run well on the Phi. In general, the bestfloating-point performance will be realized when each core isrunning two threads that actively issue instructions to the vectorunit. For a 61-core coprocessor, this means that the programmermust be able to effectively utilize 120 threads (two times of thenumber of cores minus one core reserved for the operating system)inside their application.

  Empirically, it appears that the internal Pentium cores are notfast enough to keep their associated per core vector unit busy whenrunning only one thread. Running with two threads per core appearsto be the generic minimum thread count, best performance sweetspot. This is only a general rule of thumb, as much depends on thetype and amount of work performed by each thread before it issues avector operation. (Note that future Intel Xeon Phi products willlikely support greater parallelism, so the ability to supporthigher application thread counts is highly encouraged.)

• The key to Intel Xeon Phi floating-point performance is theefficient use of the per core vector unit. To access the vectorunit, the compiler must be able to recognize SSE-compatibleconstructs so it can generate the special Intel Xeon Phi vectorinstructions. Developers with legacy code can test if theirapplications will benefit from Xeon Phi floating-point capabilityby simply telling the compiler to utilize the SSE instructions onthe current x86 processor (through the GNU –msse or other compilerswitch). Applications that run faster with SSE (or conversely slowdown when the use of SSE instructions is disabled) will likelybenefit from the Intel Xeon Phi wide vector unit. Applications thatdon’t benefit from the SSE instruction set will be limited to theperformance of the individual Pentium-based cores. Although thismeans Intel Xeon Phi will

  probably not be a performance star for non-vector applications,these coprocessors can still be used as support devices thatprovide many-core parallelism and high memory bandwidth. “

• Questions:

•  In the Flynn classification, where would you place the newXeon Phi (2 pts) ?

•  What do you thinks will be the main limit of this hardware inregards to

  performances (1 pt) ?

•  If you compare the Xeon Phi approach to what you have seenwith GPU, what will be similar and what will be different ( 2pts)

•  Prepare an abstract for this short paper (approx. 10 lines) –(5 pts).

Expert Answer

Answer to III – Excerpt of article “The preproduction Intel Xeon Phi coprocessors chips can provide well over one teraflop of…