Consider Vhdl Library Ieee Use Ieeestdlogic1164 Use Ieeenumericstd Use Ieeestdlogicunsign Q43843939
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Consider the VHDL below. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.std_logic_unsigned. all; entity my_counter is generic (N: positive := 8); port RESET : in std_logic; – reset pin CLK in std_logic; — clock input DIR in std_logic; — count direction –Y is the counter output Y : out std_logic_vector((N-1) downto @):=(others=’@’)) end entity: architecture ctr of my_counter is begin process (CLK, DIR, RESET) is variable x : unsigned ((N-1) downto O) begin – (others -> ‘); if (CLK’event and CLK = ‘1’) then if (RESET=”) then X (others -> @’); if (CLK’event and CLK = ‘1’) then if (RESET=”) then X (others => ‘0’); Y <std_logic_vector(x); else if (DIR – ‘1’) then X X + 1; else X X – 1; end if; Y = std_logic_vector(x); end if; end if; end process; end ctr; Which of the following is TRUE? Select one: a. None of the above b. When the counter reaches the maximum value. it stops counting c. There are no implicit latches in this design d. This is a counter with an asynchronous reset use. This device counts on the falling and rising edges of the clock Show transcribed image text Consider the VHDL below. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.std_logic_unsigned. all; entity my_counter is generic (N: positive := 8); port RESET : in std_logic; – reset pin CLK in std_logic; — clock input DIR in std_logic; — count direction –Y is the counter output Y : out std_logic_vector((N-1) downto @):=(others=’@’)) end entity: architecture ctr of my_counter is begin process (CLK, DIR, RESET) is variable x : unsigned ((N-1) downto O) begin – (others -> ‘); if (CLK’event and CLK = ‘1’) then if (RESET=”) then X (others -> @’); if (CLK’event and CLK = ‘1’) then if (RESET=”) then X (others => ‘0’); Y
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Answer to Consider the VHDL below. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.std_logic_unsigne…
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