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Use the following architecture for questions6-9:
Given a 3-wide in-order processor, draw theoptimal pipeline diagram and answer question 6-9, showing for eachinstruction, what stage of the pipeline it is in for each cycle forthe execution of the code sequence below. Assume full bypassing ofvalues from the respective instruction completion stage to theDecode stage. Assume that pipeline X can execute branches and ALUoperations, pipeline Y can excute loads, stores, and ALUoperations, and pipeline Z can execute loads, stores, and ALUoperations. Loads have a latency of two cycles and ALU operationshave a latency of one cycle. Branches are resolved in X0 and themachine has no branch delay slots and always predicts thefallthrough path. The machine can fetch three instructions percycle, decode three instructions per cycle, execute threeinstructions per cycle, and writeback three instructions per cyclebut maintains data dependencies. The operand steering logic cansteer any operand to any ALU to enable any instruction to reach anypipeline, but the pipelines have restrictions on what instructionseach can execute as described above. Assume that there areno alignment restrictions on instructions whichcan be simultaneously fetched from the instruction memory. Also,assume that instructions stall in the decode stage if there arestructural or data hazards and stalling one pipeline does notinhibit the fetching of future instructions. The figure below showsthe pipeline with pipeline stage names underlined.
Code sequence for questions 6-9:
Q6 ) Which instructions stall due to datahazard? Check all that apply
a) 4: ADD R14, R11, R15
b) 7: LW R22, 4(R19)
c) 8: LW R24, 8(R19)
d) 10: LW R26, 16(R19)
e) 11: OR R11, R26, R18
f) 13: ADDIU R16, R17, 3
7.Question 7
Which instructions stall due to structuralhazard? Select all that apply
a) 4: ADD R14, R11, R15
b) 7: LW R22, 4(R19)
c) 9: LW R25, 12(R19)
d) 11: OR R11, R26, R18
e) 12: AND R13, R17, R29
Q8
Which instructions stall in the fetch stage?Select all that apply
a) 6: AND R19, R20, R21
b) 7: LW R22, 4(R19
c) 11: OR R11, R26, R18
d) 12: AND R13, R17, R29
e) 13: ADDIU R16, R17, 3
Q9
Which instructions stall in the decode stage?Select all that apply
a) 4: ADD R14, R11, R15
b) 6: AND R19, R20, R21
c) 7: LW R22, 4(R19)
d) 9: LW R25, 12(R19)
e) 10: LW R26, 16(R19)
f) 11: OR R11, R26, R18
F XO, Branch Cond. X1 IRO ALU PC addr YO rdata Y1 IR1 Instr. Cache Operand ALU RF addr rdata – RF Steering Read Write Data Cache IR2 Z1 ALU addr rdata Data Cache e: ADDIU R6, R7, 1 SUBIU R9, R10, 2 R11, e(R12) R13, 0(R14) R14, R11, R15 R16, R17, R18 R19, R20, R21 R22, 4(R19) R24, 8(R19) R25, 12(R19) R26, 16(R19) R11, R26, R18 R13, R17, R29 13: ADDIU R16, R17, 3 1: 2: LW 3: LW 4: ADD 5: SUB 6: AND 7: LW 8: LW 9: LW 10: LW 11: OR 12: AND Show transcribed image text F XO, Branch Cond. X1 IRO ALU PC addr YO rdata Y1 IR1 Instr. Cache Operand ALU RF addr rdata – RF Steering Read Write Data Cache IR2 Z1 ALU addr rdata Data Cache
e: ADDIU R6, R7, 1 SUBIU R9, R10, 2 R11, e(R12) R13, 0(R14) R14, R11, R15 R16, R17, R18 R19, R20, R21 R22, 4(R19) R24, 8(R19) R25, 12(R19) R26, 16(R19) R11, R26, R18 R13, R17, R29 13: ADDIU R16, R17, 3 1: 2: LW 3: LW 4: ADD 5: SUB 6: AND 7: LW 8: LW 9: LW 10: LW 11: OR 12: AND
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