(Solved) : 42 Given Schematic Draw Timing Diagram Shows Expected Waveform Labelled Circuit Nodes Y Si Q32396021 . . .
![4.2 Given this schematic, draw a timing diagram that shows the expected waveform at each of the labelled circuit nodes A and Y SignalS Gen Assume that the signal generator was logic 0 for at least 10 ns prior to the figure, the period of the square wave is 6 ns and the propagation delay of each NAND gate is 1 ns for any transition 4.3. In a computer, a very common operation is comparing two values. This is often used to set a bit indicating that two quantities are equal or not equal. In many architectures, such as x86 and ARM, these bits are called condition codes. A conditional branch instruction uses these condition codes to determine whether to take a branch or not take a branch (fall thru). You are assigned to design the compare unit for the TriTip-8-a simple non-vegan-) 8-bit microprocessor. The compare unit takes two operands A[7:0] and B[7:0]. (Funfact-the first video game consoles, such as the Atari 2600 were based on 8-bit microprocessors) 4.3.a - Write a 2-level expression using XOR (A) and NOR for the compare function fcomp which compares two 8 bits numbers A(7:0] XPO-and B7:0] ¥F0-and evaluates to true when A(7:01 and BI7:0] match. 4.3.b - Draw a schematic using for your comparator from part a) using only 2-input XOR, 2-input OR and one final 2-input NOR gate and the minimum number of logic levels. (hint, group the terms using the associative property) 4.3.c-We can recast the answer from part b) using DeMorgans Theorem on the algebraic representation or use bubble pushing redraw your schematic using 2-input XOR, 2-input NOPR and 2-input NAND gates. Hint, your logic should take the output from the XOR and feed into a 2 input NOR gate 4.3.d The amazing success of the TriTip-8 results in a contract to build the TriTip-32, a 32-bit microprocessor. Given the following cell delays, estimate the delay for the 32-bit comparator of the TriTip-32. (show how you got your answer). Cell Tpd XOR-2 100 ps](../../../media.cheggcdn.com/media/dda/ddaeed8c-1c6e-4143-b464-713afd979804/phpFvuMqt.png)
4.2 Given this schematic, draw a timing diagram that shows the expected waveform at each of the labelled circuit nodes A and Y SignalS Gen Assume that the signal generator was logic 0 for at least 10 ns prior to the figure, the period of the square wave is 6 ns and the propagation delay of each NAND gate is 1 ns for any transition 4.3. In a computer, a very common operation is comparing two values. This is often used to set a bit indicating that two quantities are equal or not equal. In many architectures, such as x86 and ARM, these bits are called condition codes. A conditional branch instruction uses these condition codes to determine whether to take a branch or not take a branch (fall thru”). You are assigned to design the compare unit for the TriTip-8-a simple ‘non-vegan’-) 8-bit microprocessor. The compare unit takes two operands A[7:0] and B[7:0]. (Funfact-the first video game consoles, such as the Atari 2600 were based on 8-bit microprocessors) 4.3.a – Write a 2-level expression using XOR (A) and NOR for the compare function fcomp which compares two 8 bits numbers A(7:0] XPO-and B7:0] ¥F0-and evaluates to true when A(7:01 and BI7:0] match. 4.3.b – Draw a schematic using for your comparator from part a) using only 2-input XOR, 2-input OR and one final 2-input NOR gate and the minimum number of logic levels. (hint, group the terms using the associative property) 4.3.c-We can recast the answer from part b) using DeMorgan’s Theorem on the algebraic representation or use bubble pushing redraw your schematic using 2-input XOR, 2-input NOPR and 2-input NAND gates. Hint, your logic should take the output from the XOR and feed into a 2 input NOR gate 4.3.d The amazing success of the TriTip-8 results in a contract to build the TriTip-32, a 32-bit microprocessor. Given the following cell delays, estimate the delay for the 32-bit comparator of the TriTip-32. (show how you got your answer). Cell Tpd XOR-2 100 ps Show transcribed image text
Expert Answer
Answer to 42 Given Schematic Draw Timing Diagram Shows Expected Waveform Labelled Circuit Nodes Y Si Q32396021 . . .
OR